Working with the top multinational semiconductor companies around the world, ProGineer Technologies provides Physical Design (PD) services where our team works closely with analog and logic circuit designers to create the layout for the backend part of the VLSI flow.
ProGineer is working with the leading-edge technology nodes to build the best-in-class custom designs.
ProGineer delivers fully-verified, clean layout designs.
What we can do:
Create bottom-up elements of chip design including but not limited to: CMOS cell, block level custom layouts, FUB-level floor plans, abstract view generation. Our work also includes schematic to layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, layout vs schematic (LVS), design rule check (DRC), and reliability verification (RV).